A Dynamic Timing Delay for Accurate Gate-level Circuit Simulation
نویسندگان
چکیده
A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models.
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تاریخ انتشار 1996